1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device having an address space larger than 2n and smaller than 2(n+1) and to a method of controlling the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices such as flash memories, SRAMs or DRAMS each generally have an address space of 2n and a plurality of memory cells corresponding to the address space. For example, a 64M-bit flash memory comprising 16 input/output terminals (I/O=16 bit) receives address signals by 22 address terminals and controls an address space of 4M bits. By using an address space of 2n, reading and writing is carried out on the memory cells corresponding to all addresses supplied to the semiconductor memory device.
Meanwhile, with semiconductor structures becoming finer, memory capacities of semiconductor memory devices are increasing. As a result, the memory capacity of a semiconductor memory device mounted in a system unit sometimes becomes larger than the memory capacity actually used. In other words, a useless address space exists in the semiconductor memory device mounted on the system unit. In such a situation, a semiconductor memory device having an address space whose size is not 2n, where n is a positive integer, has been demanded.
For example, in the case of a semiconductor memory device having a 3M-bit address space, 22 address terminals corresponding to a 4M-bit address space are necessary. As a result, a portion of address signals indicates an invalid address not corresponding to memory cells. When an invalid address is supplied to the semiconductor memory device, error data may be output in a read operation and may be written in a memory cell in a write operation.
In Japanese Patent Application Laid-Open Publication No. Hei 7-78466, a detecting circuit for detecting a fact of invalid address signal supply is used, and a control signal for suppressing data output is generated when the fact is detected.
However, the invalid address described above is not intentionally output by the system unit mounting the semiconductor memory device, but often generated by power supply noise or an erroneous program. In this case, the system unit cannot recognize the fact that the invalid address has been supplied to the semiconductor memory device. For example, in a read operation, although the semiconductor memory device receives an invalid address and causes an input/output terminal to have high impedance, the system unit receives the level of the high-impedance state (H level in the case where a data bus is pulled up on the system) as normal data. In other words, the system unit does not operate properly only by detecting the invalid address and suppressing the data output. In order to operate normally, the system unit needs to detect the supply of the invalid address to the semiconductor memory device.
Furthermore, in the case where an invalid address is supplied to the semiconductor memory device in a write operation, data are not written in a proper address intended by the system unit. As a result, in a read operation thereafter, the system unit cannot read the data which should have been written.